PIC2550 Clockcheck
Aus Wiki_2020
Ein PIC 2550 soll mit 48MHz Taktfrequenz betrieben werden. Es wird ein 20MHz Quarzoszillator mit PLL verwendet. Als Programmierumgebung wird MPLAB X IDE mit XC8 C-Compiler eingesetzt.
Folgende Konfiguration wird verwendet:
// PIC18F2550 Configuration Bit Settings // 'C' source line config statements #include <xc.h> // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. // CONFIG1L #pragma config PLLDIV = 5 // PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input)) #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2]) #pragma config USBDIV = 1 // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale) // CONFIG1H #pragma config FOSC = HSPLL_HS // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL)) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled) #pragma config BOR = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software) #pragma config BORV = 3 // Brown-out Reset Voltage bits (Minimum setting) #pragma config VREGEN = OFF // USB Voltage Regulator Enable bit (USB voltage regulator disabled) // CONFIG2H #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit)) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected) #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected) #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected) #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected) #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected) #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected) #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
zum testen wird ein kurzes Testprogramm mit zyklischer Umschaltung PORTB Bit0 genutzt:
void main(void)
{
ConfigureOscillator();
portd_output; // PortB pins Output
while(1)
{
LATB = 0b00000000;
LATB = 0b00000001;
}
}
daraus entsteht folgender Assemblercode
!void main(void)
!{
! ConfigureOscillator();
0x7CEE: CALL 0x7CE2, 0
0x7CF0: NOP
! portd_output; // PortB pins Output
0x7CF2: MOVLW 0x0
0x7CF4: MOVWF TRISB, ACCESS
! while(1)
! {
! LATB = 0b00000000;
0x7CF6: MOVLW 0x0 // 1 Cy
0x7CF8: MOVWF LATB, ACCESS // 1 Cy
! LATB = 0b00000001;
0x7CFA: MOVLW 0x1 // 1 Cy
0x7CFC: MOVWF LATB, ACCESS // 1 Cy
0x7CFE: BRA 0x7CF6 // 2 CY
ein am entsprechenden Pin angeschlossenes MSO zeigt nun folgendes:
Fazit
Was ist daraus zu erkennen?!
48 MHz Taktfrequenz bedeutet eine Zyklusfrequenz Takt /4 ==> 12 MHz, die Programmschleife besteht aus 6 Zyklen was 24 Taktzyklen entspricht. 12 MHz Zyklusfrequenz ergibt eine Zykluszeit von 1/12MHZ = 83,33 ns (Ausführung eines 1 Zyklusbefehls dauert 83,3ns). Die Low-Zeit ergibt sich aus 2 Cy die High-Zeit sind die restlichen 4 Cy. Die Periodendauer ist somit 6*83,3ns = 499,999ns was wiederum einer Frequenz von 2MHz entspricht. Da diese Werte messtechnisch nachgewiesen wurden scheint die Konfiguration erfolgreich durchgeführt worden zu sein.
